Due to the nature of our business model, we are not currently displaying any of our customer projects publicly.
More information regarding our previous projects and experience can be obtained via non-disclosure agreement.  Contact us for more information.

System Architect

Tactical Computing Labs is currently participating with Lawrence Berkeley National Laboratory in the OpenSoC System Architect hardware and tool chain development infrastructure.  The goal of System Architect is to provide a high-level design infrastructure that provides rapid prototyping and design environment for complex SoC’s.  The target of the IP generated by the infrastructure can be ASIC-quality RTL as well as RTL targeted to one or more FPGA platforms.  Further, System Architect provides a unique ability to automatically generate the LLVM compiler backend for any and all extensions added to the core infrastructure by the users.  As a result, System Architect provides a unique ability to generate pre-verified IP and software tool chains suitable for ASIC tapeout or FPGA bitfile payloads.

For more info and release schedules for the OpenSoC System Architect infrastructure, please contact us.

xBGAS RISC-V Extension

The xBGAS project is an effort to extend the base-level RV64 RISC-V addressing model to support extended addressing modes for datacenter-scale memory access.  This project is a joint effort between Tactical Computing Laboratories, Lawrence Berkeley National Laboratory, MIT Lincoln Laboratory and Tech Tech University.

RISC-V Rev SST Model

 The Rev SST component is designed to provide cycle-based simulation capabilities of an arbitrary RISC-V core or cores. Rev utilizes the Sandia Structural Simulation Toolkit as the core parallel discrete event simulation framework. We utilize the standard SST “core” component libraries to build the Rev component. As a result, Rev can be attached to any other existing SST component for full system and network simulations.

The Rev model is unique in the scope of other SST CPU models in that is provides users the ability to load compiled binaries (ELF binaries). Rather than requiring input in the form of textual assembly or hex dumps, SST contains a RISC-V compatible loader function that generates all the necessary symbol tables and addressing modes for the target RISC-V CPU. Further, Rev permits users to generate simulation configurations that contain heterogeneous RISC-V designs with support for disparate extensions.

The Rev component infrastructure can also be extended to include custom instruction extensions. This provides users the ability to design new instruction templates without requiring modifications to the core crack+decode infrastructure. For more information on creating custom templates, see the developer documentation.

MemChameleon Lite

In an effort to support the ongoing development of both the RISC-V ecosystem and emerging memory architectures such as the Hybrid Memory Cube specification, TCL has created a software-based implementation of the HMC 2.1 packet specification based upon the SiFive Freedom SDK.  This open source firmware payload implements the entire packet specification as a payload for the Arty E310 FPGA development platform whereby the HMC I/O ports are emulated via the board’s GPIO pins.  While this doesn’t demonstrate a high performance HMC implementation, it does permit others to experiment with what may become future memory device functionality by simply adding memory operations to the firmware payload.  The MemChameleonLite firmware is open source and can be found on Github.

Community Efforts

Constructing a complete HPC system out of all open source components requires a diverse collection of tools and expertise – from advanced hardware generation technologies to compilers and programming models capable of enabling applications to fully utilize specialized hardware. One of the goals of this workshop is to bring this diverse community together to exchange ideas, present solutions and identify gaps in technology.  John Leidel, TCL Chief Scientist, is a founding member and member of the steering committee for the OpenSuCo workshop series.  For more info on the workshop goals, participants and the latest CFP, refer to the OpenSuCo website here.

IoTNet

IoTNet is building a globally distributed, crowd-sourced and open IoT data network, owned and operated by its users. Using low power, long range (LoRA wireless) technologies, IoTNet provides an end-to-end stack: from nodes, to gateways, network server, device management and integration with other IoT platforms. All fully secure and configurable by the end user to enable applications in order to fully utilize commodity hardware. Please refer to the IoTNet website here.

Project Documentation

Documentation from our open source projects can be found in the Tactical Computing Labs documentation repository.