Publications

2017

  • J.Leidel, “Bit Contiguous Memory Allocation for Processing In Memory”, MCHPC’17: Workshop on Memory Centric Programming for HPC, November 12-17, 2017, Denver, CO, USA.
  • J.Leidel, X.Wang, Y.Chen, “Pressure-Driven Hardware Managed Thread Concurrency for Irregular Applications”, IA^3’17: IA^3’17: Seventh Workshop on Irregular Applications: Architectures and Algorithms, November 12-17, 2017, Denver, CO, USA.
  • X.Wang, J.D.Leidel, Y.Chen, “OpenMP MemKind: An Extension for Heterogeneous Physical Memories”, International Workshop on Parallel Programming Models and Systems Software for High-End Computing (P2S2), August 2017, Bristol, United Kindgom.
  • J.Leidel, Y.Chen, “HMC-Sim-2.0: A co-design infrastructure for exploring custom memory cube operations”, Journal of Parallel Computing, October 2017.
  • J.Leidel, X.Wang, Y.Chen, “Toward a Memory-Centric, Stacked Architecture for Extreme-Scale Data Intensive Computing”, Workshop on Pioneering Processor Paradigms (WP^3), High Performance Computing Architecture Conference, January 2017, Austin, Texas.
  • J. Leidel, Y.Chen, D.Donofrio, F.Fatallahi-Fard. OpenSoC System Architect: An Open Toolkit for Building High Performance SoC’s. 2017 Design Automation Conference Poster Session. Austin, Texas, June 2017.

2016

  • X. Wang, J.Leidel, Y.Chen, “Dynamic Memory Coalescing of Irregular Memory Workloads for Hybrid Memory Cube Devices”, The 2016 International Symposium on Memory Systems (MEMSYS), October 2016, Washington, DC.
  • J.Leidel, Y.Chen, “Exploring Tag-Bit Memory Operations in Hybrid Memory Cubes”, The 2016 International Symposium on Memory Systems (MEMSYS), October 2016, Washington, DC.
  • J.Leidel, Y.Chen, “HMC-Sim 2.0: A Simulation Platform for Exploring Custom Memory Cube Operations”, Sixth International Workshop on Accelerators and Hybrid Exascale Systems (AsHES), May 2016, Chicago, Illinois.
  • X.Wang, J.Leidel, Y.Chen. Concurrent Dynamic Memory Coalescing on GoblinCore-64 Architecture. 2016 Supercomputing Technical Poster Session. Salt Lake City, UT. November 2016.

2015

  • J.Leidel and Y.Chen. Toward Memory Centric Architecture Simulation for Data Intensive Applications. 2015 Multiagency Workshop on Modeling and Simulation of Systems and Applications. Seattle, Washington, August 2015.
  • J.Leidel, Y.Chen, “Communication Avoiding Power Scaling”, Eighth International Workshop on Parallel Programming Models and Systems Software for High-End Computing (P2S2), September 2015, Beijing, China.

2014

  • J.Leidel, Y.Chen, “HMC-SIM: A Simulation Framework for Hybrid Memory Cube Devices”, Journal of Parallel Processing Letters, December 2014.
  • J.Leidel, Y.Chen, “HMC-SIM: A Simulation Framework for Hybrid Memory Cube Devices”, in press, 2014 Large-Scale Parallel Processing Workshop, 19 May, 2014, Phoenix, AZ.

Capabilities

Micro architecture, architecture evaluation, graph theory, machine learning, sparse linear algebra, cryptography. These are all areas where Tactical Computing Laboratories has unique expertise and experience.

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Current Projects

We participate with Lawrence Berkeley National Laboratory in the OpenSoC System Architect hardware and tool chain development infrastructure.

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About Us

Our experience in designing advanced computing platforms for computationally-intensive and data-intensive workloads has proven this time and time again.

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